Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2010-0037524 filed onApr. 22, 2010, the disclosure of which is hereby incorporated in itsentirety by reference, is claimed.

BACKGROUND OF THE INVENTION

An embodiment of the present invention relates to a semiconductor deviceand a method for manufacturing the same.

Recently, as the data storage capacity of semiconductor memory deviceshas increased and the integration level has also increased, the size ofeach unit cell has been required to become smaller. As the integrationof the semiconductor device becomes higher, a distance between a gateand a bit line connected to a cell transistor becomes closer. As aresult, parasitic capacitance increases to a decrease in the operatingreliability of the semiconductor device. In order to improve thereliability of the semiconductor device, a buried-type gate structurehas been suggested. In the buried-type gate structure, a conductivematerial is formed in a recess formed in a semiconductor substrate, andthe upper portion of the conductive material is covered with aninsulating film so that a gate may be buried in the semiconductorsubstrate. As a result, electric separation between a bit line and a bitline contact plug formed on the semiconductor substrate is more clearlydefined. A semiconductor device comprising of the buried-type gate and amethod for manufacturing the same are described as follows.

FIG. 1 is a layout diagram illustrating a conventional semiconductordevice.

Referring to FIG. 1, a semiconductor device includes a cell region I anda peripheral region II. In a cell region I, a device isolation structure13 that defines an active region 15 is formed, and a plurality of gates25 and a plurality of bit lines (not shown) are formed. The gate 25 is aburied gate, and a bit line contact plug 30 is formed on the activeregion 15 between the gates 25. The bit line (not shown) that contactswith the bit line contact plug 30 is formed perpendicular to the gate25.

FIGS. 2 a and 2 b are cross-sectional diagrams illustrating theconventional semiconductor device and a method for manufacturing thesame, which show cross-sectional views taken along a-a′ of FIG. 1.

Referring to FIG. 2 a, a semiconductor substrate 10 including the cellregion I and the peripheral region II is etched to form a trench fordevice isolation that defines the active region 15. The trench (notshown) is filled with an oxide film to form the device isolationstructure 13. One integrated device isolation structure 13 is formed ina boundary section between the cell region I and the peripheral regionII. The device isolation structure 13 and the active region 15 of thecell region I are etched to form a recess. A gate oxide film (not shown)and a barrier metal layer (not shown) are formed on the resultantsurface including the recess. The barrier metal layer (not shown)includes a titanium nitride (TiN) film. A conductive material 20 isburied in the lower portion of the recess having the barrier metal layer(not shown). The conductive material 20 includes tungsten. A firstsealing nitride film 23 is formed on the resultant structure includingthe recess filled with the conductive material 20 to form a buried-typegate 25.

Referring to FIG. 2 b, the first sealing nitride film 23 is etched toform a bit line contact hole, and the bit line contact hole is filledwith a conductive material to form a bit line contact plug 30. A secondsealing nitride film 35 is formed on the resultant structure includingthe bit line contact plug 30. A mask pattern (not shown) that opens theperipheral region II is formed on the upper portion of the secondsealing nitride film 35. The first sealing nitride film 23 and thesecond sealing nitride film 35 of the peripheral region II are removedusing the mask pattern as a mask.

A gate oxidation process for forming a gate is performed on theperipheral region II to form a gate oxide film 40. The mask pattern (notshown) is removed. A process for forming a bit line is performed on thecell region I, and a process for forming a gate is performed on theperipheral region II.

Since the gate oxidation process is performed on the peripheral regionII after the buried-type gate 25 is formed in the cell region I, oxygenions generated from the oxidation process may move along an oxidationpath as shown by path ‘A’ in FIG. 2 b. As a result, the TiN film whichis a barrier metal layer (not shown) of the buried-type gate 25 isoxidized. The oxidation of the barrier metal layer causes a gate oxideintegrity (GOI) fail and an unlimited sensing delay (USD) fail.

In order to prevent the GOI fail and the USD fail, an overlap betweenthe buried-type gate and the peripheral circuit open mask of the cellregion requires an overlap of at least 640 nm or more, and a distancebetween the gates of the peripheral region of the open mask requires aspace of at least 740 nm or more. A distance between the buried-typegate of the cell region and the gate of the peripheral region requires aspace of at least 1380 nm or more. However, as the minimum distancebetween the cell region and the peripheral region increases, the size ofa die also increases, which results in a decrease in the number of diesper wafer, thereby reducing the cost efficiency.

BRIEF SUMMARY OF THE INVENTION

Various embodiments of the invention are directed to forming an activeregion that serves as a guard ring along a boundary part of a cellregion and a peripheral region and forming a buried gate or a bit linecontact in the active region so that the cell region may have a completesealing structure, thereby improving characteristics of thesemiconductor device.

According to an embodiment of the present invention, A semiconductordevice including a cell region and a peripheral region, thesemiconductor device comprising: a guard ring region provided betweenthe cell region and the peripheral region, the guard ring region havinga barrier structure.

The barrier structure has a shape of a buried-type gate. The barrierstructure includes a conductive material and an insulating film providedwithin a trench defined in a guard ring region. The conductive materialincludes tungsten, a titanium nitride film and combinations thereof. Theinsulating film includes a nitride film.

The insulating film is formed on an upper portion of the guard ringregion and the cell region. The barrier structure is a plug formed onthe guard ring region. The plug has substantially the same dimension asa bit-line contact plug formed on the cell region. The plug includes oneselected from the group consisting of a polysilicon layer, a metal layerand a combination thereof.

According to an embodiment of the present invention, A method formanufacturing a semiconductor memory device, the method comprising:providing a substrate having a cell region, a guard ring region, and aperipheral region, the guard ring region provided between the cellregion and the peripheral region; etching a recess in the guard ringregion to form a recess; filling conductive material into the recess;and depositing an insulating film within the recess over the conductivematerial in order to form a barrier structure in the guard ring region.

The conductive material includes one selected from the group consistingof tungsten, a titanium nitride film and a combination thereof. Theinsulating film includes a nitride film, and the insulating film isdeposited over the peripheral region and the guard ring region while theinsulating film is being deposited within the recess, the method furthercomprising: removing a portion of the insulating film overlying theperipheral region with a mask that exposes only the peripheral region.

The barrier structure is formed simultaneously with a gate in the cellregion. The guard ring region encloses perimeters of the cell region.

According to an embodiment of the present invention, A method formanufacturing a semiconductor device, the method comprising: forming aguard ring region between a cell region and a peripheral region;depositing an insulating film over the cell region, guard ring region,and the peripheral region; etching the insulating film to form a contacthole to expose a portion of the guard ring region; depositing conductivematerial within the contact hole to form a contact plug; and removingthe insulating film overlying the peripheral region to open theperipheral region, wherein the contact plug is formed at the same time abit-line contact plug is being formed in the cell region.

The contact plug is a dummy contact plug and is configured to float. 17.The insulating film includes a nitride film. The conductive materialincludes one selected from the group consisting of a polysilicon layer,a metal layer and a combination thereof. The contact plug is configuredto prevent oxygen particles from migrating into the cell region. Theinsulating film is deposited when the buried-type gate is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout diagram illustrating a conventional semiconductordevice.

FIGS. 2 a and 2 b are cross-sectional diagrams illustrating theconventional semiconductor device.

FIG. 3 is a layout diagram illustrating a semiconductor device accordingto an embodiment of the present invention.

FIGS. 4 a to 4 h are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to an embodiment of thepresent invention.

FIGS. 5 a to 5 h are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to another embodiment ofthe present invention.

DESCRIPTION OF EMBODIMENTS

The present invention will be described in detail with reference to theattached drawings.

FIG. 3 is a layout diagram illustrating a semiconductor device accordingto an embodiment of the present invention.

Referring to FIG. 3, a semiconductor device includes a cell region I anda peripheral region II. In the cell region I, a device isolationstructure 103 that defines a first active region 105 is formed, and aplurality of first gates 125 a are formed in the first active region105. The first gate 125 a may be a buried-type gate, but is not limitedthereto. In the first active region 105, two first gates 125 a can beformed. A bit line contact plug 130 is formed on the first active region105 between the first gates 125 a. A bit line (not shown) that contactsthe bit line contact plug 130 is formed perpendicular to the first gate125 a.

A second active region 107 that serves as a guard ring is formed betweenthe cell region I and the peripheral region II. In the second activeregion (or a guard ring region) 107, a second gate 125 b is formed. Thesecond gate 125 b may be a buried-type gate having substantially thesame structure as that of the first gate 125 a. In an embodiment of thes present invention, the second gate 125 b not included in the activeregion 107, but a bit line contact plug is included in the upper portionof the active region 107. The second gate 125 b in the second activeregion 107 serves as a guard ring structure to prevent oxygen ions frompermeating from the peripheral region II into the cell region I.

FIGS. 4 a to 4 h are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to an embodiment of thepresent invention, which show cross-sectional views taken along a-a′ ofFIG. 3.

Referring to FIG. 4 a, a semiconductor substrate 100 including the cellregion I and the peripheral region II is etched to form a first trenchfor device isolation. After the first trench is filled with an oxidefilm, a planarizing process is performed to form a device isolationstructure 103. The device isolation structure 103 defines the firstactive region 105 in the cell region I, the second active region 107 atthe border of the cell region I and the peripheral region II, and athird active region 105 in the peripheral region II. The second activeregion 107 is formed between the first active region 105 in the cellregion I and the third active region 105 in the peripheral region II.

Unlike a conventional art where the cell region I and the peripheralregion II are in direct contact with each other, the cell region I andthe peripheral region II are separated from each other by the secondactive region 107.

Referring to FIG. 4 b, an oxide pattern 110 that defines a gate regionis formed on the upper portion of the semiconductor substrate 100including the device isolation structure 103. The gate region is alsodefined on the upper portion of the active region 107 formed between thecell region I and the peripheral region II. A device isolation structure103 in the cell region I, the first active region 105 in the cell regionI and the second active region 107 are etched using the oxide pattern110 as a mask to form a first recess 115 a in the first active region105 and the device isolation structure 103 in the cell region I and asecond recess 115 b in the second active region 107. The depth of thefirst and the second recesses 115 a and 115 b is made different by anetching selectivity difference between the device isolation structure103 including an oxide film and the first and the second active regions105, 107 including a silicon material.

Referring to FIG. 4 c, a gate oxidation process is performed onto thecell region Ito form a gate oxide film over the first recess 115 a and115 b in the second active region 107. A barrier metal layer (not shown)is formed on the oxide pattern 110 including the recesses 115 a and 115b. The barrier metal layer (not shown) can include a TiN film and canhave a thickness ranging from about 50 to about 70 Å. A conductivematerial 120 is formed on the upper portion of the oxide pattern 110including the recesses 115 a and 115 b. The conductive material 120 maybe formed of tungsten, a TiN film or a combination thereof. Theconductive material 120 may include tungsten W, which is formed to havea thickness ranging from about 1400 to about 1600 Å by a chemical vapordeposition (CVD) method.

Referring to FIG. 4 d, a chemical mechanical polishing (CMP) process isperformed to expose the oxide pattern 110, thereby planarizing theconductive material 120. The upper portion of the oxide pattern 110 canbe partially removed by the CMP process. The conductive material 120 isfurther etched by an etch-back process, so that the conductive material120 has a shape having a given depth removed from the top side of thefirst and the second recesses 115 a and 115 b. The conductive material120 has a thickness ranging from about 600 to about 800 Å which remainsat the bottom part of the first and is second recesses 115 a and 115 b.

Referring to FIGS. 4 e and 4 f, a first sealing nitride film 123 isdeposited on the upper portion of the semiconductor substrate 100including the first and the second recesses 115 a and 115 b which arepartially filled with the conductive material 120, thereby forming afirst buried-type gate 125 a in the cell region I and a secondburied-type gate 125 b in the second active region 107. The secondburied-type gate 125 b is a dummy gate used as a barrier structure toprevent impurities or undesirable particles (e.g., oxygen ions) frompermeating into the cell region I from the peripheral region II. Thefirst sealing nitride film 123 is formed to fill the first and thesecond recesses 115 a and 115 b. The first sealing nitride film 123 hasa thickness ranging from about 600 to about 800 Å. The secondburied-type gate 125 b formed in the second active region 107 may beformed with substantially the same width as that of the firstburied-type gate 125 a formed in the cell region I. The width can beadjusted depending on a process margin for the peripheral region II.

A mask pattern (not shown) that defines a bit line contact region isformed on the upper portion of the first sealing nitride film 123. Themask pattern (not shown) can be formed of carbon, a silicon oxidenitride (SiON) film or a combination thereof. The first sealing film 123is etched using the mask pattern (not shown) to form a bit line contacthole. The mask pattern (not shown) is also removed at this time. The bitline contact hole is formed to expose the semiconductor substrate 100 atone side of the first gate 125 a formed in the first active region 105.Material such as a polysilicon layer, a metal layer or a combinationthereof is formed on the resultant surface including the bit linecontact hole. An etch-back process is performed to form a bit linecontact plug 130 filling up the bit line contact hole.

Referring to FIG. 4 g, a second sealing nitride film 135 is deposited onthe first sealing nitride film 123 including the bit line contact plug130. The second sealing nitride film 135 is deposited at a thicknessranging from about 100 to about 300Å. Referring to FIG. 4 g, a maskpattern (not shown) that opens the peripheral region II is formed on theupper portion of the second sealing nitride film 135. The oxide pattern110, the first sealing nitride film 123 and the second sealing nitridefilm 135 formed in the peripheral region II are etched away using themask pattern (not shown).

The mask pattern (not shown) which opens the peripheral region II isformed to overlap a portion of the second buried-type gate 125 b formedin the second active region 107 so that the second buried-type gate 125b will not be fully exposed.

A gate oxidation process is performed to form a gate oxide film 140 overthe semiconductor substrate 100 in the peripheral region II. The gateoxidation process is performed to form a third gate(not shown) in theperipheral region II.

As mentioned above, the second active region 107 is formed between thecell region I and the peripheral region II. The second buried-type gate125 b is formed in the active region 107 to separate the cell region Ifrom the peripheral region II (see ‘B’ of FIG. 4 h). In a gate oxidationprocess for forming the gate oxide film 140 in the peripheral region II,the second buried-type gate 125 b prevents oxygen ions from permeatinginto the cell region I and thus prevents oxidation of the TiN film. TheTiN film is formed as a barrier metal layer (not shown) of the firstburied-type gate 125 a formed in the cell region I. That is, anoxidation path in the substrate 100 from the peripheral region II intothe cell region I is blocked by the active region 107 and the secondburied-type gate 125 b, thereby preventing degradation of the cellregion I performance.

FIGS. 5 a to 5 h are cross-sectional diagrams illustrating a method formanufacturing a semiconductor device according to another embodiment ofthe present invention, which shows cross-sectional views taken alonga-a′ of FIG. 3.

Referring to FIG. 5 a, the semiconductor substrate 100 of a cell regionI and a peripheral region II is etched to form a trench for deviceisolation that defines a first active region 105 in the cell region I, asecond active region 107 between the cell region I and the peripheralregion II, and a third active region 105 in the peripheral region II.After the trench (not shown) is filled with an oxide film, aplanarization process is performed to form the device isolationstructure 103. The second active region 107 for separating the cellregion I from the peripheral region II is formed at the border of thecell region I and the peripheral region II.

Referring to FIG. 5 b, the oxide pattern 110 that defines a gate regionis formed on the upper portion of the semiconductor substrate 100including the device isolation structure 103. The gate region is definedin the cell region I but not in the second active region 107 or in theperipheral region II. The device isolation structure 103 and the activeregion 105 in the cell region I are etched using the oxide pattern 110as a mask to form a first recess 115.

Referring to FIG. 5 c, the gate oxidation process is performed on thecell region I to form a gate oxide film (not shown) in the first recess115. A barrier metal layer (not shown) is formed on the surface of theoxide pattern 110 including the recess 115. The barrier metal layer (notshown) can be formed of a TiN film and have a thickness ranging fromabout 50 to about 70 Å. The conductive material 120 is formed over theoxide pattern 110 including the first recess 115. The conductivematerial 120 can be selected from tungsten, a TiN film and a combinationthereof. For example, the conductive material 120 may be formed oftungsten W which is formed by a CVD method with a thickness ranging fromabout 1400 to about 1600 Å.

After a CMP process is performed to expose the oxide pattern 110, theconductive material 120 is further etched by an etch-back process sothat the conductive material fills the lower portion of the first recess115. The conductive material 120 remains to have a thickness rangingfrom about 600 to about 800 Å from the lower portion of the first recess115.

Referring to FIG. 5 d, a first sealing nitride film 123 is formed on theupper portion of the semiconductor substrate 100 including the firstrecess 115. The first sealing nitride film 123 is formed to fill theupper portion of the first recess 115 to form a buried-type gate 125.The first sealing nitride film 123 has a thickness ranging from about600 to about 800 Å. Referring to FIG. 5 e, a mask pattern (not shown)that defines a bit line contact region is formed on the upper portion ofthe first sealing nitride film 123. The mask pattern (not shown) can beformed of carbon, a SiON film or a combination thereof.

The first sealing nitride film 123 is etched to form a first bit linecontact hole 127 a in the first active region 105 and then the maskpattern (not shown) is removed. The bit line contact hole 127 a isformed to expose the semiconductor substrate 100 at one side of the gate125 in the first active region 105. A second bit line contact hole 127 bis also formed in the second active region 107 formed between the cellregion I and the peripheral region II.

Referring to FIG. 5 f, a layer such as a polysilicon layer, a metallayer and a combination thereof is formed on the upper portion of thefirst sealing nitride film 123 including the first and the second bitline contact holes 127 a and 127 b. An etch-back process is performed toform a first and a second bit line contact plug 130 a and 130 b. Thewidth of the second bit line contact plug 130 b formed in the secondactive region 107 may be formed to be identical to the first bit linecontact plug 130 a formed in the first active region 105 of the cellregion I. However, the width may be adjusted depending on a processmargin of the adjacent peripheral region II. The second bit line contactplug 130 b formed in the second active region 107 blocks a path throughwhich oxygen can permeate from the peripheral region II into the cellregion I in a subsequent oxidation process. In the present embodiment,the second bit line contact plug 130 b is a dummy bit-line contact plugthat serves as a barrier structure to prevent oxygen ions or particlesfrom migrating into the cell region I from the peripheral region II.

Referring to FIGS. 5 g and 5 h, a second sealing nitride film 135 isdeposited on the upper portion of the first sealing nitride film 123including the first and second bit line contact plugs 130 a and 130 b. Amask pattern (not shown) which opens the peripheral region II is formedon the upper portion of the second sealing nitride film 135. The oxidepattern 110, the first sealing nitride film 123 and the second sealingnitride film 135 of the peripheral region II are patterned using themask pattern (not shown) as a barrier. The mask pattern (not shown) thatopens the peripheral region II is formed to overlap a portion the bitline contact plug 130 b formed on the guard ring active region 107 sothat the bit line contact plug 130 b formed on the guard ring activeregion 107 may not be exposed. However, a portion of the bit linecontact plug 130 b may be exposed but the whole bit line contact plug130 b may not be exposed.

A gate oxidation process is performed to form a gate oxide film 140 onthe second sealing nitride film 135 of the cell region I and on thesurface of the semiconductor substrate 100 of the peripheral region II.The gate oxidation process is performed to form a gate of the peripheralregion II.

The second active region 107 is formed between the cell region I and theperipheral region II. The second bit line contact plug 130 b is formedin the second active region 107 (see ‘C’ of FIG. 5 h). In the gateoxidation process for forming the gate oxide film 140 in the peripheralregion II, an oxidation path from the peripheral region II into the cellregion I is blocked and thus the TiN film serving as a barrier metallayer (not shown) and forming of the buried-type gate 125 of the cellregion I can be protected from undesired oxidation. That is, theoxidation path in the lower portion of the semiconductor substrate 100can be blocked by the second active region 107, and the oxidation pathin the upper portion of the semiconductor substrate 100 can be blockedby the second bit line contact plug 130 b.

As described above, a semiconductor device and a method formanufacturing the same according to an embodiment of the presentinvention may prevent oxidation of a buried-type gate formed in a cellregion and also prevent GOI fail and USD fail resulting from theoxidation of the buried-type gate, thereby improving yield of thesemiconductor device. Also, a sufficient distance between theburied-type gate of the cell region and a gate of a peripheral regioncan be ensured.

The above embodiments of the present invention are illustrative and notlimitative. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching polishing,and patterning steps describe herein. Nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention may be implemented in a dynamic random access memory (DRAM)device or non volatile memory device. Other additions, subtractions, ormodifications are obvious in view of the present disclosure and areintended to fall within the scope of the appended claims.

1. A semiconductor device including a cell region and a peripheralregion, the semiconductor device comprising: a guard ring regionprovided between the cell region and the peripheral region, the guardring region having a barrier structure.
 2. The semiconductor deviceaccording to claim 1, wherein the barrier structure has a shape of aburied-type gate.
 3. The semiconductor device according to claim 2,wherein the barrier structure includes a conductive material and aninsulating film provided within a trench defined in a guard ring region.4. The semiconductor device according to claim 3, wherein the conductivematerial includes any of tungsten, a titanium nitride film and acombination thereof.
 5. The semiconductor device according to claim 3,wherein the insulating film includes a nitride film.
 6. Thesemiconductor device according to claim 1, wherein the insulating filmis formed on an upper portion of the guard ring region and the cellregion.
 7. The semiconductor device according to claim 1, wherein thebarrier structure is a plug formed on the guard ring region.
 8. Thesemiconductor device according to claim 7, wherein the plug hassubstantially the same dimension as a bit-line contact plug formed onthe cell region.
 9. The semiconductor device according to claim 7,wherein the plug includes one selected from the group consisting of apolysilicon layer, a metal layer and a combination thereof. 10.-20.(canceled)